1. Field of the Invention
The present invention generally relates to the design and manufacture of integrated circuits, and more particularly to a method of wire routing an integrated circuit design having multiple layers.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for vertical and/or horizontal routing: the polysilicon layer, and the metal-1, metal-2, and metal-3 layers.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins, including information about the various components such as transistors, resistors and capacitors. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The process of converting the specifications of an electrical circuit into such a layout is called the physical design.
Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA), including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Physical synthesis is prominent in the automated design of integrated circuits such as high performance processors and application specific integrated circuits (ASICs). Physical synthesis is the process of concurrently optimizing placement, timing, power consumption, crosstalk effects and the like in an integrated circuit design. This comprehensive approach helps to eliminate iterations between circuit analysis and place-and-route. Physical synthesis has the ability to repower gates (changing their sizes), insert repeaters (buffers or inverters), clone gates or other combinational logic, etc., so the area of logic in the design remains fluid. However, physical synthesis can take days to complete.
Routability is a key factor when performing circuit floorplanning or trying to close on timing via physical synthesis. A designer can expend considerable effort trying to get the design into a good state in terms of timing and signal integrity, only to subsequently find that it is unroutable. Ideally, the designer should be able to invoke a snapshot routability analysis that allows him or her to understand the routability issues involved from making floorplanning or optimization decisions.
Routing is further complicated in circuit designs having a building-block hierarchy, wherein the circuit can be considered logically as a top level having cells or nodes which are each constructed from sub-blocks, and the sub-blocks may themselves be constructed of smaller sub-blocks at lower levels. Designers currently run automatic routers at each level of the circuit hierarchy separately. While quicker than a complete manual layout, this approach still requires excessive time and preparation on the part of the designer, especially in setting up blockage patterns to prevent the router from using all available metal layers at lower level cells in the hierarchy. This approach also increases the runtime required by layout checking tools such as layout versus schematic, design rule checks, and methodology checks. These problem are exacerbated in particularly large designs.
It would, therefore, be desirable to devise an improved routing method to speed up turnaround time and decrease computational cost. It would be further advantageous if the method could take into consideration all levels of a hierarchical layout to ensure sufficient metal at upper level cells to complete the routes automatically.